Emulated Hardware

RAM map:

  Addr (bytes)
╔════════════╤══════════════╗
║ 0x00000000   Start of RAM ║
║      .     │              ║
║ 0x000E7F00   DISPLAY_START║
║      .     + 0x18000 bytes║
║      .     or 0x6000 words║
║      .    or 1024x768x1px ║
║ 0x000FFF00  end of display║
║      .     │              ║
║ 0x00180000   MemSize      ║
╟──────────  ┼  ────────────╢
║            │              ║
║          Empty            ║
╟──────────  ┼  ────────────╢
║ 0xFFFFF800   ROMStart     ║
║      .     │              ║
║      .       IO_RANGE     ║
║ 0xFFFFFFC0 | clock        ║
║ 0xffffffc4 | switches/LEDs║
║ 0xffffffc8 | serial data  ║
║ 0xffffffcc | serial status║
║ 0xffffffd0 | SPI data     ║
║ 0xffffffd4 | SPI control  ║
║ 0xffffffd8 | mouse        ║
║      .     │              ║
╚════════════╧══════════════╝
class oberon.risc.ByteAddressed32BitRAM[source]

Represent a 32-bit wide RAM chip that is byte-addressed.

E.g. addresses 0-3 are the first four bytes, or one (32-bit) word.

BYTE_MASKS = (4294967040, 4294902015, 4278255615, 16777215)
get(addr)[source]

Return a (32-bit) word. Address must be word-aligned.

get_byte(addr)[source]

Return a byte. Address need not be word-aligned.

put(addr, word)[source]

Set a (32-bit) word. Address must be word-aligned.

put_byte(addr, byte)[source]

Set a byte. Address need not be word-aligned.

class oberon.risc.Clock(now=None)[source]

clock

read()[source]
reset(now=None)[source]
time()[source]

Return int time in ms.

write(word)[source]
class oberon.risc.DataControl(spi)[source]
read()[source]
write(word)[source]
class oberon.risc.Disk(image_file)[source]

(I cribbed most of this from pdewacht/oberon-risc-emu . I’m not exactly sure how it works but it does work, well enough to load the Oberon OS from the disk image.)

SECTOR_SIZE = 512
SECTOR_SIZE_WORDS = 128
STRUCT_FORMAT = '<128I'
diskCommand = 0
diskRead = 1
diskWrite = 2
diskWriting = 3
read()[source]
read_sector(into=0)[source]
run_command()[source]
write(word)[source]
write_sector()[source]
class oberon.risc.FakeSPI[source]

SPI

read()[source]
register(index, thing)[source]
write(word)[source]
class oberon.risc.Keyboard(initial_keys=())[source]

pdewacht/oberon-risc-emu/blob/master/src/sdl-ps2.c

read()[source]
class oberon.risc.LEDs[source]
read()[source]
write(word)[source]
class oberon.risc.Mouse[source]
button_down(n)[source]
button_up(n)[source]
read()[source]
set_coords(x, y)[source]
write(word)[source]
class oberon.risc.RISC(rom, ram, PC=1073741312)[source]

The RISC processsor.

This class is designed for ease of introspection rather than efficiency.

Arithmetic_Logical_Unit()[source]

Enact the ALU of the RISC chip.

branch_instruction()[source]

Branch instruction.

brief_view()[source]

Debug function, print crude state of chip.

cycle()[source]

Run one cycle of the processor.

decode(instruction)[source]

Decode the instruction and set various field and flag member values of the emulator object.

dump_mem(to_file=None, number=10, syms=None)[source]
dump_ram(to_file=None, location=None, number=10, syms=None)[source]

Debug function, print a disassembly of a span of RAM.

dump_rom(to_file, location=None, number=10)[source]

Debug function, print a disassembly of a span of ROM.

fetch()[source]

Load an instruction from RAM or ROM and return it. Raise Trap if PC goes out of bounds or if the machine enters a certain kind of infinite loop (this is a way for code running on the emulated chip to signal HALT.)

io(port)[source]

I/O instruction.

ram_instruction()[source]

RAM read/write instruction.

register_instruction()[source]

Increment PC and set a register from the ALU.

set_register(value)[source]

Set A register and N, Z, and H.

view()[source]

Debug function, print current instruction.

class oberon.risc.Serial(input_file)[source]
read()[source]
write(word)[source]
class oberon.risc.SerialStatus(ser)[source]
read()[source]
write(word)[source]
exception oberon.risc.Trap[source]
oberon.risc.log(message, *args)[source]