Emulated Hardware

class oberon.risc.ByteAddressed32BitRAM[source]

Represent a 32-bit wide RAM chip that is byte-addressed.

E.g. addresses 0-3 are the first four bytes, or one (32-bit) word.

get(addr)[source]

Return a (32-bit) word. Address must be word-aligned.

get_byte(addr)[source]

Return a byte. Address need not be word-aligned.

put(addr, word)[source]

Set a (32-bit) word. Address must be word-aligned.

put_byte(addr, byte)[source]

Set a byte. Address need not be word-aligned.

class oberon.risc.Clock(now=None)[source]

clock

time()[source]

Return int time in ms.

class oberon.risc.Disk(image_file)[source]

(I cribbed most of this from pdewacht/oberon-risc-emu . I’m not exactly sure how it works but it does work, well enough to load the Oberon OS from the disk image.)

class oberon.risc.FakeSPI[source]

SPI

class oberon.risc.LEDs[source]
class oberon.risc.Mouse[source]
class oberon.risc.RISC(rom, ram, PC=1073741312)[source]

The RISC processsor.

This class is designed for ease of introspection rather than efficiency.

Arithmetic_Logical_Unit()[source]

Enact the ALU of the RISC chip.

branch_instruction()[source]

Branch instruction.

brief_view()[source]

Debug function, print crude state of chip.

cycle()[source]

Run one cycle of the processor.

decode(instruction)[source]

Decode the instruction and set various field and flag member values of the emulator object.

dump_ram(to_file=None, location=None, number=10, syms=None)[source]

Debug function, print a disassembly of a span of RAM.

dump_rom(to_file, location=None, number=10)[source]

Debug function, print a disassembly of a span of ROM.

fetch()[source]

Load an instruction from RAM or ROM and return it. Raise Trap if PC goes out of bounds or if the machine enters a certain kind of infinite loop (this is a way for code running on the emulated chip to signal HALT.)

io(port)[source]

I/O instruction.

ram_instruction()[source]

RAM read/write instruction.

register_instruction()[source]

Increment PC and set a register from the ALU.

set_register(value)[source]

Set A register and N, Z, and H.

view()[source]

Debug function, print current instruction.

exception oberon.risc.Trap[source]